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PREFACE 1 INTRODUCTION 1.1 STRUCTURED COMPUTER ORGANIZATION 1.2 MILESTONES IN COMPUTER ARCHITE 1.3 THE COMPUTER ZOO 1.4 EXAMPLE COMPUTER FAMILIES 1.5 OUTLINE OF THIS BOOK 2 COMPUTER SYSTEMS ORGANIZATION 2.1 PROCESSORS 2.2 PRIMARY MEMORY 2.3 SECONDARY MEMORY 2.4 INPUT/OUTPUT 2.5 SUMMARY 3 THE DIGITAL LOGIC LEVEL 3.1 GATES AND BOOLEAN ALGEBRA 3.2 BASIC DIGITAL LOGIC CIRCUITS 3.3 MEMORY 3.4 CPU CHIPS AND BUSES 3.5 EXAMPLE CPU CHIPS 3.6 EXAMPLE BUSES 3.7 INTERFACING 3.8 SUMMARY 4 THE MICROARCHtTECTURE LEVEL 4.1 AN EXAMPLE MICROARCHITECTURE 4.2 AN EXAMPLE ISA: IJVM 4.3 AN EXAMPLE IMPLEMENTATION 4.4 DESIGN OF rHE MICROARCHITECTURE LEVEL 4.5 IMPROVING PERFORMANCE 4.6 EXAMPLES OF THE MICROARCHITECTURE LEVEL 4.7 SUMMARY 5 THE INSTRUCTION SET ARCHITECTURE LEVEL 5.1 OVERVIEW OF THE ISA LEVEL 5.2 DATA TYPES 5.3 INSTRUCTION FORMATS 5.4 ADDRESSING 5.5 INSTRUCTION TYPES 5.6 FLOW OF CONTROL 5.7 A DETAILED EXAMPLE: THE TOWERS OF HANOI 5.8 THE INTEL IA-64 5.9 SUMMARY 6 THE OPERATING SYSTEM MACHINE LEVEL 6.1 VIRTUAL MEMORY 6.2 VIRTUAL UO INSTRUCTIONS 6.3 VIRTUAL INSTRUCTIONS FOR PARALLEL PROCESSING 6.4 EXAMPLE OPERATING SYSTZMS 6.5 SUMMARY 7 THE ASSEMBLY LANGUAGE LEVEL I 7.1 INTRODUCTION TO ASSEMBLY LANGUAGE 7.2 MACROS 7.3 THE ASSEMBLY PROCESS 7.4 LINKINO AND LOADING 7.5 SUMMARY 8 PARALLEL COMPUTER ARCHITECTURES 8.1 DESIGN ISSUES FOR PARALLEL COMPUTERS 8.2 SIMD COMPUTERS 8.3 SHARED-MEMORY MULTIPROCESSORS 8.4 MESSAGE-PASSING MULTICOMPUTERS 8.5 SUMMARY 9 READING LIST AND BIBLIOeRAPHY 9.1 SUGGESTIONS FOR FURTHER READING 9.2 ALPHABETICAL BIBLIOORAPHY A BINARY NUMBERS A.1 FINITE-PRECISION NUMBERS A.2 RADIX NUMBER SYSTEMS A.3 CONVERSION FROM ONE RADIX TO ANOTHER A.4 NEGATIVE BINARY NUMBERS A.5 BINARY ARnHMETIC B FLOATING－POINT NUMBERS B.1 PRINCIPLES OF FLOATING POINT B.2 IEEE FLOATING-POINT STANDARD INDEX